Vertical power component

ABSTRACT

A vertical power component includes a doped silicon substrate of a first conductivity type. A local well of a second conductivity type extends from an upper surface of the substrate. A passivation structure coats a peripheral region of the upper surface side of the substrate surrounding the well. This passivation structure includes, on top of and in contact with the peripheral substrate region, a first region made of a first passivation material and a second region made of a second passivation material. The second region generates, in a surface region of the substrate in contact with said second region, a local increase of the concentration of majority carriers in the substrate.

CROSS REFERENCE TO RELATED APPLICATIONS

This application is a divisional of U.S. application patent Ser. No.15/362,919 filed November 29, 2016, which claims the priority benefit ofFrench Application for Patent Nos. 1652823 and 1652824, filed Mar. 31,2016, the disclosures of which are hereby incorporated by reference.

TECHNICAL FIELD

The present disclosure relates to a vertical semiconductor powercomponent capable of withstanding a high voltage in the off state, andmore specifically aims at the structure of the periphery of such acomponent.

BACKGROUND

Various ways to form the periphery of a vertical power component, inorder to protect the component edges, and in particular to provide ahigh breakdown voltage of the component and to limit leakage currentshave been provided.

Known peripheral structures of vertical power component however havedisadvantages.

There is accordingly a need in the art for a peripheral structure of avertical power component overcoming all or part of the disadvantages ofknown structures.

SUMMARY

Thus, an embodiment provides a vertical power component comprising: adoped silicon substrate of a first conductivity type; a local well ofthe second conductivity type extending from an upper surface of thesubstrate; and on the upper surface side of the substrate, a passivationstructure coating a peripheral region of the substrate surrounding thewell, said passivation structure comprising, on top of and in contactwith said peripheral substrate region, a first region made of a firstpassivation material and a second region made of a second passivationmaterial, the second region being capable of generating, in a surfaceregion of the substrate in contact with said second region, a localincrease of the concentration of majority carriers in the substrate.

According to an embodiment, the second region is made of phosphosilicateglass.

According to an embodiment, the second region is made of a materialcapable of generating fixed positive charges at the interface withsilicon.

According to an embodiment, the second region is made of semi-insulatingpolysilicon.

According to an embodiment, the second region is made of siliconnitride.

According to an embodiment, the first region is made of silicon oxide.

According to an embodiment, the first region is made of lead glass.

According to an embodiment, one of the first and second regions of thepassivation structure is a layer coating said peripheral region of thesubstrate, interrupted by a ring-shaped opening arranged opposite acentral portion of said peripheral region of the substrate, the otherregion of the passivation structure being a ring-shaped strip arrangedin said opening.

Another embodiment provides a method of manufacturing a vertical powercomponent inside and on top of a doped silicon substrate of a firstconductivity type, comprising the steps of: forming a local well of thesecond conductivity type extending from an upper surface of thesubstrate; and forming, on the upper surface side of the substrate, apassivation structure coating a peripheral region of the substratesurrounding the well, said passivation structure comprising, on top ofand in contact with said peripheral substrate region, a first regionmade of a first passivation material and a second region made of asecond passivation material, the second region being capable ofgenerating, in a surface region of the substrate in contact with saidsecond region, a local increase of the concentration of majoritycarriers in the substrate.

According to an embodiment, the second region is made of phosphosilicateglass, the forming of the second region comprising a step of depositingphosphosilicate glass at the surface of said peripheral region of thesubstrate, followed by a step of annealing at a temperature higher than500° C.

According to an embodiment, the second region is made of semi-insulatingpolysilicon, the forming of the second region comprising a step ofdepositing semi-insulating polysilicon at the surface of said peripheralregion of the substrate, followed by a step of annealing at atemperature in the range from 200 to 400° C. or at a temperature higherthan 700° C.

According to an embodiment, the second region is made of siliconnitride, the forming of the second region comprising a step ofdepositing the second region comprising a step of depositing siliconnitride at the surface of said peripheral region of the substrate, bychemical vapor deposition under a gas flow comprising a mixture ofsilane and of ammonia, with a ratio R of the ammonia content to thesilane content in the mixture smaller than 100 or greater than 900.

BRIEF DESCRIPTION OF THE DRAWINGS

The foregoing and other features and advantages will be discussed indetail in the following non-limiting description of specific embodimentsin connection with the accompanying drawings, wherein:

FIG. 1 is a cross-section view of an example of a vertical powercomponent;

FIG. 2 is a cross-section view of an example of a vertical powercomponent according to a first embodiment; and

FIG. 3 is a cross-section view of an example of a vertical powercomponent according to a second embodiment.

DETAILED DESCRIPTION

The same elements have been designated with the same reference numeralsin the different drawings and, further, the various drawings are not toscale. For clarity, only those elements which are useful to theunderstanding of the described embodiments have been shown and aredetailed. In particular, the various uses which may be made of avertical power component have not been detailed, the describedembodiments being compatible with usual applications of vertical powercomponents, for example, the control of motors, or the control ofhousehold appliances such as refrigerator compressors, vacuum cleaners,air conditioning units, washing machines, etc. In the followingdescription, when reference is made to terms qualifying absolutepositions, such as terms “front”, “rear”, “top”, “bottom”, “left”,“right”, etc., or relative positions, such as terms “above”, “under”,“upper”, “lower”, etc., or to terms qualifying directions, such as terms“horizontal”, “vertical”, etc., it is referred to the orientation of thedrawings, it being understood that, in practice, the describedcomponents may be oriented differently. Unless otherwise specified,expressions “approximately”, “substantially”, and “in the order of” meanto within 10%, preferably to within 5%.

In the present description, vertical power component means a componentcomprising first and second conduction electrodes arranged on oppositesurfaces of a silicon substrate, the component being capable, in the offstate, of withstanding a high voltage, for example, higher than 100 Vand typically higher than 500 V, between its first and second conductionelectrodes. Vertical power switches capable of withstanding highvoltages between their conduction terminals whatever the biasing of theapplied voltage, also called bidirectional voltage switches, are hereconsidered. Switches bidirectional for voltage may be bidirectional forcurrent, for example, triacs, or one-way for current, for example,thyristors or some IGBTs.

FIG. 1 is a cross-section view of a vertical power component,illustrating a way of forming the periphery of such a component inso-called “planar” technology to protect the component edges.

The component shown in the present example is a triac. It comprises anN-type doped silicon substrate 1 (N⁻) and extending in substrate 1 fromits upper surface, a local P-type doped well 3 (P). Well 3 extends, intop view, over a portion only of the surface of substrate 1, forexample, over more than half the surface of substrate 1. Well 3 isarranged in a non-peripheral portion of substrate 1, that is, it doesnot extend all the way to the periphery of substrate 1. The component ofFIG. 1 further comprises, extending in substrate 1 from the lowersurface thereof, a P-type doped layer 5 (P). Layer 5 extends, in bottomview, over substantially the entire surface of substrate 1. Moreparticularly, layer 5 extends all the way to a P-type doped peripheralinsulating wall 11 (P), described in further detail hereafter.

Upper layer 3 contains, on its upper surface side, an N-type dopedregion 4 (N⁺), having a higher doping level than substrate 1. Lowerlayer 5 contains, on its lower surface side, an N-type doped region 6(N⁺), having a higher doping level than substrate 1, for example havingsubstantially the same doping level as region 4, located in an areasubstantially complementary (in top view) to that occupied by region 4.Upper well 3 further contains, on its upper surface side, an N-typedoped region 8 (N⁺), non-adjacent to region 4, having a higher dopinglevel than the substrate, for example, substantially of same dopinglevel as region 4.

On the lower surface side of the component, a conduction electrode A2coats and is in contact with substantially the entire surface of layer5. On the upper surface side of the component, a conduction electrode A1coats and is in contact with region 4 and a portion of well 3. ElectrodeA1 is, however, not in contact with the peripheral region of substrate 1surrounding well 4. Further, on the upper surface side of the component,a gate electrode G separate from electrode A1 coats and is in contactwith region 8 and a portion of well 3.

On the upper surface side of the component, an insulating passivationlayer 9 made of silicon oxide coats the portions of the upper surface ofthe substrate which are not covered with electrodes, and in particularthe PN junction between well 3 and substrate 1 and the peripheral regionof substrate 1 surrounding well 3. Silicon oxide layer 9 may be toppedwith other passivation layers, not shown, which may be inorganic (forexample, silicon nitride) or organic (for example, based on polyimides).

Whatever the polarity of the voltage applied between electrodes A2 andA1, if a gate control signal is provided, the component turns on. Theconduction is performed from electrode A2 to electrode A1 by a verticalthyristor comprising regions 5, 1, 3, and 4, or from electrode A1 toelectrode A2 by a vertical thyristor comprising regions 3, 1, 5, and 6.The thickness and the doping level of substrate 1 are calculated so thatthe triac, in the off state, can withstand high voltages, for example,voltages in the range from 600 to 800 volts.

In the shown example, the triac is entirely surrounded with a P-typedoped diffused wall 11 (P) formed from the lower and upper surfaces ofthe substrate and extending across the entire thickness of thesubstrate. On the lower surface side of the component, layer 5 extendslaterally all the way to diffused wall 11, and on the upper surfaceside, well 3 stops before diffused wall 11. Wall 11 particularly has thefunction of insulating the lateral surfaces of substrate 1 and of thusavoiding possible short-circuits of the component by solder wicking whenlower electrode A2 of the component is welded to a contact area of anexternal device.

To avoid for breakdowns to occur at the component edges, a certaindistance should be provided between the limit of P-type well 3 anddiffused wall 11.

Given the relative instability of the interface between the siliconoxide of layer 9 and the silicon of substrate 1 (interface states, hotelectrons, etc.), the component further comprises an N-type dopedchannel stop ring 13 (N+), having a higher doping level than substrate1, for example having substantially the same doping level and the samedepth as region 4, arranged in peripheral substrate region 1 locatedbetween well 3 and wall 11 (non-adjacent to well 3 and to wall 11 in theshown example). Channel stop ring 13 extends in substrate 1 from theupper surface thereof and surrounds, in top view, well 3. Channel stopring 13 enables to prevent the forming of a parasitic P-type channel inthe substrate surface area located under the silicon oxide layer 9. Inthe absence of channel stop ring 13, such a parasitic channel may inparticular appear in conditions of high instability of the siliconoxide/oxide interface states, typically when the component is kept inthe off state at a relatively high temperature. The provision of channelstop ring 13 enables both to improve the breakdown voltage of thecomponent and to decrease leakage currents. As a variation, not shown,to uniformize the potential all over ring 13, ring 13 may be contactedalong its entire length by a floating metallization (not connected)arranged in an opening previously formed in layer 9 and emerging on theupper surface of ring 13.

As an example, substrate 1 has a doping level in the range from 10¹⁴ to2*10¹⁴ atoms/cm³, P-type doped regions 3, 5, and 11 have a doping levelin the range from 10¹⁸ to 10¹⁹ atoms/cm³, and N-type doped regions 4, 6,8, and 13 have a doping level in the range from 10¹⁹ to 2*10²⁰atoms/cm³.

In practice, it can be observed that the presence of channel stop ring13 results in degrading the switching performance of the component. Sucha degradation especially results from the fact that the channel stopring forms, around the active portion of the component, a peripheralring-shaped path where the electron mobility is high, which results inunwanted electron transfers between the first thyristor, formed byregions 5, 1, 3, and 4 (left-hand portion of the drawing) and the secondthyristor, formed by regions 3, 1, 5, and 6 (right-hand portion of thedrawing), causing a degradation of the switching performance of theswitch.

FIG. 2 is a cross-section view of an example of a vertical powercomponent.

FIG. 2 shows a triac comprising the same elements as the triac of FIG.1, except for channel stop ring 13. In the embodiment of FIG. 2, siliconoxide passivation layer 9 is discontinuous. More particularly, layer 9is interrupted by a ring-shaped opening surrounding (in top view) well3, this opening being arranged opposite a central portion of theperipheral substrate region 1 surrounding well 3, and having a widthsmaller than that of said peripheral substrate region. The ring-shapedopening formed in passivation layer 9 is filled with a secondpassivation material, a phosphosilicate glass (PSG) in the example ofFIG. 2. Thus, silicon oxide layer 9 coating the peripheral region ofsubstrate 1 is interrupted by a ring-shaped phosphosilicate glass strip21, arranged on top of an in contact with the upper surface of theperipheral region of substrate 1 surrounding well 3. In the shownexample, for reliability reasons, phosphosilicate glass is furtherdeposited over substantially the entire surface of silicon oxide layer9. In other words, ring-shaped strip 21 is a portion of a largerphosphosilicate glass layer 22 substantially coating the entire surfaceof layer 9 and being in contact with the upper surface of substrate 1 atthe level of the ring-shaped opening formed in layer 9.

The method of manufacturing the passivation structure of FIG. 2comprises:

forming silicon oxide passivation layer 9, for example, by thermaloxidation of the upper surface of substrate 1;

forming, in layer 9, a through ring-shaped opening surrounding (in topview) well 3;

depositing a phosphosilicate glass to fill the opening previously formedin silicon oxide layer 9; and

after the deposition of the phosphosilicate glass in the opening, astabilization anneal, for example, at a temperature greater than 500°C., for example, at a temperature in the order of 900° C.

During the stabilization anneal, phosphorus atoms originating from thephosphosilicate glass diffuse from ring-shaped strip 21 into a substratesurface region located under ring-shaped strip 21, for example, down toa depth in the range from 10 to 100 nm from the upper surface of thesubstrate. This amounts to performing a slight N-type overdoping of thesubstrate surface region located under ring-shaped passivation strip 21.Electrons thus accumulate in the surface region of substrate 1 locatedunder ring-shaped step 21. Such a local accumulation of electronsprevents the forming of a parasitic P-type channel in the peripheralregion of substrate 1 surrounding well 3. Due to the small depth of thesubstrate surface region impacted by the N-type overdoping, and/or dueto the relatively low surface density of electrons, for example, in therange from 5*10¹⁵ to 5*10¹⁶ e⁻/cm², for example, in the order of 10¹⁶e⁻/cm², in this region, the mobility of electrons in this region remainsrelative small as compared with the mobility of electrons in channelstop ring 13 of the component of FIG. 1. Thus, the passivation structureof FIG. 2 ensures a good breakdown voltage of the component and limitsleakage currents, while avoiding the degradation of the switchingperformances observed in structures of the type described in relationwith FIG. 1. In practice, the depth of the phosphorus doping as well asthe dopant concentration is a function of the temperature and of theduration of the stabilization anneal, as well as of the phosphoruscontent of the phosphosilicate glass, for example, in the range from 2to 10%.

FIG. 3 is a cross-section view of an example of a vertical powercomponent.

FIG. 3 shows a triac. The triac of FIG. 3 differs from the triac of FIG.2 essentially in that, in the example of FIG. 3, the phosphosilicateglass ring-shaped passivation strip 21 of the triac of FIG. 2 has beenreplaced with a ring-shaped passivation ring 31 made of a passivationmaterial capable of generating stable fixed positive charges at theinterface with silicon, and accordingly of generating an accumulation ofelectrons in the surface region of substrate 1 located under ring-shapedstrip 31. Here again, this prevents the forming of a parasitic P-typechannel in the peripheral region of substrate 1 surrounding well 3, andthus to enables to benefit from a good voltage behavior and decreasedleakage currents. Further, due to the small depth, for example, in therange from 1 to 25 nm, of the substrate surface region where theelectrons accumulate, and/or due to the relatively low electron density,for example, in the range from 5*10¹⁸ to 5*10¹⁹ e⁻/cm³, for example, inthe order of 10¹⁸ e⁻/cm³, in this region, the electron mobility remainsrelatively low as compared with the electron mobility in channel-stopring 13 of the component of FIG. 1. Thus, the passivation structure ofFIG. 3 enables to improve the switching performance as compared with astructure of the type described in relation with FIG. 1. In practice,the depth of the electron accumulation area and the electron densitydepends on the charge concentration at the interface, for example, inthe range from 10¹¹ to 10¹³, for example, in the order of 10¹²charges/cm². In the same way as in the example of FIG. 2, in the shownexample, for reasons of reliability, the second passivation material isfurther deposited over substantially the entire surface of silicon oxidelayer 9. In other words, ring-shaped strip 31 is a portion of a largerlayer 32 of the second passivation material, substantially coating theentire surface of layer 9 and being in contact with the upper surface ofsubstrate 1 at the level of the ring-shaped opening formed in layer 9.

As an example, the second passivation material forming ring-shaped strip31 is SIPOS (Semi-Insulating Polycrystalline Silicon), or siliconnitride. Examples of methods enabling to form a SIPOS or silicon nitridelayer on a silicon substrate, to generate fixed positive charges at theSIPOS/silicon or nitride/ silicon interface, are described in “Thecorrelation between the breakdown voltage of power devices passivated bysemi-insulating polycrystalline silicon and the effective density ofinterface charges” of Edmund P. Burte and Gunter H. Schulze, IEEETransactions on Electron Devices 38(6):1505-1509, July 1991(incorporated by reference). As an example, ring-shaped strip 31 is madeof SIPOS and the passivation structure manufacturing method comprises:

forming silicon oxide passivation layer 9, for example, by thermaloxidation of the upper surface of substrate 1;

forming, in layer 9, a through ring-shaped opening surrounding (in topview) well 3;

depositing SIPOS to fill the opening previously formed in silicon oxidelayer 9; and

after the SIPOS deposition, performing a stabilization anneal at atemperature in the range from 200 to 400° C., for example, in the orderof 300° C., or at a temperature greater than 700° C., for example, inthe order of 900° C.

As an example, ring-shaped strip 31 is made of silicon nitride and thepassivation structure manufacturing method comprises:

forming silicon oxide passivation layer 9, for example, by thermaloxidation of the upper surface of substrate 1;

forming, in layer 9, a through ring-shaped opening surrounding (in topview) well 3; and

depositing silicon nitride to fill the opening previously formed insilicon oxide layer 9, by chemical vapor deposition under a gas flowcomprising a mixture of silane (SiH₄) and ammonia (NH₃), with a ratio Rof the ammonia content to the silane content in the mixture smaller than100 or greater than 900.

Specific embodiments have been described. Various alterations,modifications, and improvements will occur to those skilled in the art.In particular, in the embodiments of FIGS. 2 and 3, silicon oxide layer9 may be replaced with a layer of another passivation material, forexample, glass capable of generating fixed negative charges at theinterface with silicon, for example, lead glass.

Further, in FIG. 2, the passivation materials of layer 9 and ofring-shaped strip 21 may be inverted. Similarly, in FIG. 3, thepassivation materials of layer 9 and of ring-shaped strip 31 may beinverted.

Further, the described embodiments may be adapted to components formedinside and on top of a P-type doped silicon substrate 1. In this case,all conductivity types may be inverted. The second passivation material,respectively forming ring-shaped strip 21 in the example of FIG. 2 andring-shaped strip 31 in the example of FIG. 3, will then be selected togenerate a hole accumulation in the underlying substrate surface area,to prevent the forming of an N-type channel in the peripheral region ofsubstrate 1 surrounding well 3.

Thus, a common point between the above-described embodiments is that thepassivation structure coating the peripheral region of substrate 1surrounding well 3 comprises an alternation of two regions made ofdifferent passivation materials, one of the two materials being capableof generating, in a surface area of substrate 1 in contact with thematerial, an accumulation or a local overconcentration of carriers ofthe same type as the majority carriers in substrate 1, that is,electrons in the case of an N-type substrate, and holes in the case of aP-type substrate. Passivation material here means an insulating orsemi-insulating material, for example, having an electric conductivitysmaller than 10⁻⁸ S.cm⁻¹ at 25° C.

Further, the above-described embodiments may be adapted to verticalpower components other than triacs, for example, thyristors,transistors, IGBTs, etc.

Further, the described embodiments are not limited to the shown exampleswhere the component comprises a diffused wall extending at the componentperiphery across the entire substrate thickness.

Such alterations, modifications, and improvements are intended to bepart of this disclosure, and are intended to be within the spirit andthe scope of the present invention. Accordingly, the foregoingdescription is by way of example only and is not intended to belimiting. The present invention is limited only as defined in thefollowing claims and the equivalents thereto.

1. A vertical power component, comprising: a doped silicon substrate ofa first conductivity type; a local well of a second conductivity typeextending from an upper surface of the doped silicon substrate; and onthe upper surface of the doped silicon substrate, a passivationstructure coating a peripheral region of the doped silicon substratesurrounding the local well, said passivation structure comprising, ontop of and in contact with said peripheral substrate region, a firstregion made of a first passivation material and a second region made ofa second passivation material, the second region providing, in a surfaceregion of the doped silicon substrate in contact with said secondregion, a local increase of concentration of majority carriers in thedoped silicon substrate.
 2. The component of claim 1, wherein the secondregion is made of phosphosilicate glass (PSG).
 3. The component of claim1, wherein the first region is made of silicon oxide.
 4. The componentof claim 1, wherein the first region is made of lead-filled glass. 5.The component of claim 1, wherein one of the first and second regions ofthe passivation structure is a layer coating said peripheral region ofthe doped silicon substrate, interrupted by a ring-shaped openingarranged opposite a central portion of said peripheral region of thedoped silicon substrate, the other region of the passivation structurebeing a ring-shaped strip arranged in said opening.
 6. A method ofmanufacturing a vertical power component inside and on top of a dopedsilicon substrate of a first conductivity type, comprising the steps of:forming a local well of a second conductivity type extending from anupper surface of the doped silicon substrate; and forming, on the uppersurface side of the doped silicon substrate, a passivation structurecoating a peripheral region of the doped silicon substrate surroundingthe local well, said passivation structure comprising, on top of and incontact with said peripheral substrate region, a first region made of afirst passivation material and a second region made of a secondpassivation material, the second region providing, in a surface regionof the doped silicon substrate in contact with said second region, alocal increase of the concentration of majority carriers in the dopedsilicon substrate.
 7. The method of claim 6, wherein the second regionis made of phosphosilicate glass, the forming of the second regioncomprising a step of depositing phosphosilicate glass at the surface ofsaid peripheral region of the doped silicon substrate, followed by astep of annealing at a temperature higher than 500° C.